What “28 nm” or “3 nm” really means

Chip announcements often lead with a number followed by "nm": 28 nm, 7 nm, 3 nm, 2 nm. It sounds like a measurement, and for a long time it was. Today it is mostly a name. Knowing the difference helps explain where the industry's money goes and why India's first fab starts where it does.

Where node names came from

From the 1970s into the 1990s, a process node was named after a real dimension, roughly the length of the transistor gate or half the distance between repeated lines. A "0.5 micron" process printed features about half a micron wide. Each new node shrank that dimension by about 0.7 times, which halved the area of a transistor and roughly doubled how many fit on a chip. That steady doubling is what people mean by Moore's Law.

From the late 1990s, the names and the physical dimensions drifted apart. Engineers found other ways to improve density and performance, such as new materials and new transistor shapes, and the industry kept the naming rhythm going. No feature on a "3 nm" chip is 3 nanometres across. The distance between neighbouring transistor gates on such a process is closer to 50 nm, and the tightest metal lines sit a little over 20 nm apart.

A node name tells you the generation of a process, not the size of anything on the chip.

Because companies name their nodes differently, one firm's "7 nm" and another's "10 nm" have at times offered similar density. A more useful comparison is transistor density, measured in millions of transistors per square millimetre, along with speed and power at a given design.

How the transistor changed shape

Each change gave the gate better control over current as dimensions shrank, which reduced leakage and let designers keep cutting power.

Leading edge and mature nodes

The industry broadly splits nodes into two groups.

Leading-edge nodes, today roughly 5 nm and below, are used for the highest-performance chips: smartphone processors, data centre CPUs and AI accelerators. They need EUV lithography, where a single scanner costs well over $150 million, and a fab costs $20 billion or more. Only a handful of companies make chips at these nodes.

Mature nodes, usually defined as 28 nm and above, make the majority of chips by unit volume. They cover microcontrollers in cars and appliances, power management chips, display drivers, analog and sensor chips, and connectivity chips. These products do not benefit from extreme density. They need reliability, voltage handling and low cost, and they stay in production for many years.

The shortage of 2021–22 that idled car plants around the world was largely a shortage of mature-node chips. That experience changed how governments and carmakers think about where these chips come from.

Why India is starting at 28–110 nm

Tata Electronics and PSMC's fab at Dholera is planned around 28, 40, 55, 90 and 110 nm, for power management ICs, display drivers, microcontrollers and computing logic. Several reasons make this a sound starting point:

• Demand. India's own markets for vehicles, electronics, power and telecom consume large volumes of exactly these chips.
• Capital and risk. A mature-node fab costs a fraction of a leading-edge one, and the processes are proven.
• Equipment access. These nodes use deep ultraviolet lithography and widely available tools, without depending on the most restricted equipment.
• Learning. Running a fab well is a skill built over years: yield ramp, maintenance, supply chain, talent. Mature nodes are where that skill is built.

Mature-node fabs are not easy. Margins are thinner and competition is strong, so cost, uptime and yield decide who makes money. That makes the supporting ecosystem, covered in Part 5, especially important.