Inside a fab: how a wafer becomes a chip

A semiconductor fab is a factory, but an unusual one. A single product moves through hundreds of tools, takes two to three months to finish, and is ruined by a speck of dust smaller than a bacterium. This part walks through what happens to a wafer between arriving as polished silicon and leaving as a grid of finished chips.

The cleanroom

The production floor of a fab is a cleanroom. Air is filtered and pushed downward through the ceiling in a constant flow, so particles are carried away from the work. People wear full gowns, hoods, masks and gloves, because human skin and breath are among the largest sources of contamination.

In modern 300 mm fabs, wafers rarely touch cleanroom air at all. They travel in sealed pods called FOUPs (front-opening unified pods), carried along overhead rails by automated vehicles, and open only inside the clean mini-environment of each tool. The environment inside a FOUP and a tool is far cleaner than any room a person could work in.

Below the cleanroom sits the subfab: pumps, chemical delivery, gas cabinets, abatement systems and water treatment that feed the tools above and treat what they exhaust. Above it run air handling and filtration. A fab is really three floors of infrastructure stacked around one floor of production.

The core loop: build a layer, check it, repeat

A chip is built up in layers, like a very precise multi-storey building. Each layer is made by repeating a small set of process types in different combinations.

1. Deposition

A thin film is added to the wafer surface: an insulator such as silicon dioxide, a conductor such as tungsten or copper, or silicon itself. Methods include chemical vapour deposition (CVD), physical vapour deposition or sputtering (PVD), atomic layer deposition (ALD), which builds films one atomic layer at a time, and thermal oxidation in furnaces.

2. Lithography

Lithography prints the pattern. The wafer is coated with a light-sensitive photoresist, then exposed to light through a mask (also called a reticle) that carries the circuit pattern for that layer. The exposed resist is developed away, leaving a stencil on the wafer. Deep ultraviolet scanners use 193 nm light; the most advanced layers use extreme ultraviolet (EUV) at 13.5 nm. Lithography is usually the most expensive step and sets how small features can be.

3. Etch

Etching removes material wherever the resist does not protect it, transferring the pattern into the film below. Most critical etching is done with plasma (dry etch), which cuts straight down with very little sideways spread. Wet etching with liquid chemicals is used where precision matters less.

4. Implant and diffusion

To create n-type and p-type regions, ion implanters fire dopant atoms into the silicon at controlled energies and doses. A heat treatment called annealing then repairs the crystal damage and activates the dopants.

5. CMP and clean

Each new layer leaves the surface uneven. Chemical mechanical planarisation (CMP) polishes it flat with a slurry and a rotating pad, so the next layer can be printed in focus. Between almost every step the wafer is cleaned, often with ultrapure water and high-purity chemicals, to remove particles and residues.

6. Metrology and inspection

After key steps, wafers are measured and inspected: film thickness, the width of printed lines, how well each layer lines up with the one below, and whether there are defects. This is how a fab knows its process is under control before problems multiply across thousands of wafers. Part 6 covers why this matters so much to a fab's economics.

Front end and back end of line

Fab engineers divide the process into two halves. The front end of line (FEOL) builds the transistors themselves in and on the silicon. The back end of line (BEOL) builds the wiring that connects them: layer after layer of copper lines and vias separated by insulators. A complex logic chip can have more than a dozen metal layers, and the wiring often takes as many steps as the transistors.

What it takes to run

A fab uses enormous quantities of utilities. It consumes millions of litres of ultrapure water a day, cleaned to a level far beyond drinking water. It needs a steady supply of bulk gases such as nitrogen, plus dozens of specialty gases and chemicals of extreme purity. Its power supply must be stable, because a brief dip can scrap every wafer in process. And it needs systems to treat exhaust gases and wastewater before they leave the site.

The tools come from a small group of specialised equipment makers. ASML dominates lithography. Applied Materials, Lam Research and Tokyo Electron lead in deposition, etch and cleaning. KLA leads in process control: inspection, metrology and the software that analyses their data.

Leaving the fab

At the end of the line, each chip on the wafer is tested electrically by a probe card that touches its contact pads. This wafer sort step marks which dies work. The wafer then leaves the fab for assembly and test, where it is cut into individual chips and packaged. That is the subject of Part 3.